Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

ldswp.shRd, Rp[disp] 

temp[15:0] = *(Rp+SE(disp12) << 1);
Rd = SE(temp[7:0], temp[15:8]);
 
{d, p} ∈ {0, 1, …, 15}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

111

Rp

11101

Rd

0010

disp12

3

4

5

4

4

12

2

ldswp.uhRd, Rp[disp] 

temp[15:0] = *(Rp+SE(disp12) << 1);
Rd = ZE(temp[7:0], temp[15:8]);
 
{d, p} ∈ {0, 1, …, 15}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

111

Rp

11101

Rd

0011

disp12

3

4

5

4

4

12

3

ldswp.wRd, Rp[disp] 

temp = *(Rp+SE(disp12) << 2);
Rd = (temp[7:0], temp[15:8], temp[23:16], temp[31:24]);
 
{d, p} ∈ {0, 1, …, 15}
disp ∈ {-8192, -8188, ..., 8188}

Rev1+

111

Rp

11101

Rd

1000

disp12

3

4

5

4

4

12

Description

This instruction loads a halfword or a word from memory. If a halfword load is performed, the loaded value is zero- or sign-extended. The bytes in the loaded value are shuffled and the result is written back to Rd. The instruction can be used for performing loads from memories of differ- ent endianness.

Status Flags:

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected